1. Field of the Invention
The present invention relates to a semiconductor memory device. The invention relates more particularly to the control of bit lines at a time of a read operation in a NAND flash memory.
2. Description of the Related Art
A NAND flash memory is composed of, for example, a memory cell array, a sense amplifier, and bit lines which electrically connect the memory cell array and the sense amplifier. A plurality of memory cells, each including a charge accumulation layer and a control gate electrode, are disposed in the memory cell array.
In recent years, with an increase in information amount, there has been an increasing demand for the expansion of memory capacity.
This demand has conventionally been met by increasing the number of memory cell arrays. Various methods have been adopted in order to suppress an increase in power consumption due to the expansion of the memory capacity (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2006-79803).
However, if the demand for the expansion of the memory capacity is to be satisfied while the area of occupation of the NAND flash memory is being kept at a present level, it is necessary to make the memory cells still finer. To make the memory cells finer leads to degradation in characteristics of the memory cells. In addition, long bit lines are required. The increase in length of bit lines leads to an increase in parasitic resistance and parasitic capacitance of bit lines. As a result, there occurs such a problem that the data read speed of the NAND flash memory lowers.